A lower electrode of a capacitor, which contacts a drain or a source of an access transistor in the prior art stacked capacitor DRAM, is formed in the form of one layer.
FIG. 3 is a cross sectional view showing a structure of a memory cell of the prior art stacked capacitor DRAM. In order to manufacture the memory cell of DRAM, an SiO.sub.2 film 12 is selectively formed on a surface of a P type Si substrate 11 to form a field region, and then an SiO.sub.2 film 13 is formed as a gate oxide film on a surface of an active region. Then, a polycide film 16 consisting of a polycrystalline Si film 14 and WSi.sub.x film 15 is formed on the SiO.sub.2 films 13 and 12 by performing the patterning to form a gate electrode, i.e., a word line.
Next, ions of N type impurities are implanted into the active region at low concentration with the polycide film 16 and the SiO.sub.2 film 12 as a mask, and then a sidewall of the polycide film 16 is formed of an SiO.sub.2 film 17 or the like. Thereafter, ions of N type impurities are implanted into the active region at high concentration with the polycide film 16 and the SiO.sub.2 films 12 and 17 as a mask to form diffusion regions 21 and 22. Up to this process, an access transistor 23 having a LDD (lightly doped drain) structure is formed.
Next, an interlayer insulating film 24 is formed on the whole surface of the substrate body, and then a contact hole 25 is formed through the interlayer insulating film 24 so as to reach the diffusion region 21. Then, a polycrystalline Si film 26 is deposited on the whole surface of the substrate body so as to contact the diffusion region 21 through the contact hole 25, and then N type impurities are introduced into the polycrystalline Si film 26. This introduction is performed by the ion implantation, the solid phase diffusion or the like. Thereafter, the polycrystalline Si film 26 is processed into a pattern of a lower electrode.
Next, a capacitor dielectric film 27 made of an insulating material such as an ONO film, and a polycrystalline Si film 31 are formed in this order on the whole surface of the substrate body, and then the impurities are introduced into the polycrystalline Si film 31. Thereafter, the polycrystalline Si film 31 is processed into a pattern of an upper electrode. Up to this process, a stacked capacitor 32 is formed.
Thereafter, an interlayer insulating film 33 is formed on the whole surface of the substrate body, and then a contact hole 34 is formed through the interlayer insulating films 33 and 34 so as to reach the diffusion region 22. Then, the patterning is performed to form a bit line (not shown) which contacts the diffusion region 22 through the contact hole 34, and then an over coat film and the like (not shown) are formed thereby to complete the stacked capacitor DRAM.
For example, Kobayashi discloses in JP-A-3-44068 stacked capacitor DRAM in which an electrode is formed into an irregular shape to increase the area of the electrode and to increase the capacitance of the capacitor. In this connection, the lower electrode of the stacked capacitor by Kobayashi is also made of a polysilicon film of one layer which was doped with phosphorus.
However, if phosphorus is employed as the N type impurities which are to be introduced into the polycrystalline Si film 26, since a diffusion coefficient of phosphorus is large, as shown in FIG. 2, the junction of the diffusion region 21 becomes deep. Thus, if the junction of the diffusion region 21 becomes deep, the resistance to the soft error due to the radiation of the .alpha.-rays, and the characteristics of the access transistor 23 are degraded. On the other hand, if arsenic having a small diffusion coefficient is introduced into the polycrystalline Si film 26, the junction of the diffusion region 21 becomes shallow. However, it is well known that when arsenic is employed, the film quality of the capacitor dielectric film 27 formed on the polycrystalline Si film 26 is degraded.
That is, in the above-mentioned prior art structure, it is impossible to prevent the degradation of the film quality of the capacitor dielectric film 27 while preventing the degradation of the resistance to the soft error and the degradation of the characteristics of the access transistor 23.